1. Field of the Invention
The present invention relates to the field of scan testing; more particularly, the present invention relates to a method and apparatus for performing scan testing that reduces the number of scan cells required to achieve high test coverage.
2. Description of Related Art
A typical integrated circuit has combinational logic blocks which are coupled through latches controlled by a system clock. In many designs, the system clock has multiple phases wherein each phase is used to enable corresponding latches. In order to test the functionality and performance of a combinational logic block, various combinations of stimulus conditions are selected according to well-known methods.
Scan testing is a well-known technique for implementing multiple scan cells that are serially coupled to produce a scan chain. The scan chain serially accepts data that is applied to inputs of combinational logic blocks. The ability to directly control inputs simplifies the preparation process for a test of the combinational logic blocks. Each scan cell is also coupled to sample an output of a combinational logic block and serially shift the sampled value out of the scan chain to be compared with expected values.
To perform scan testing, a sequence of bits are applied to the head of the scan chain until all the scan cells have been initialized to the proper value, the bits are then applied to the corresponding combinational logic block, and the response is captured by a scan cell and shifted out for comparison with expected responses. Fault coverage of a test database is a measure of the percentage of modeled faults that are detectable using that test database to test the operation of a device.
Full scan devices, such as a level sensitive scan design (LSSD), include scan cells at the inputs and outputs of each combinational block. Combinational test generation techniques are then applied to generate test patterns to exercise each of the combinational blocks to provide high fault coverage. The use of scan cells at every input and output of a combinational block requires increased die area which adds to the cost of the device.
Partial scan devices use scan cells at selected inputs and outputs of each combinational block. Therefore, there may be multiple combinational blocks active in different phases of a clock signal to form a sequential circuit between each scan cell. Sequential test generation techniques are then used to exercise each of the sequential circuits between scan cells. Sequential test generation is more complex than combinational test generation. Some inputs to a combinational block may only be controllable by scanning in data to other scan cells and performing a sequence of operations to propagate the desired effect to the desired non-scan cell. Furthermore, some outputs of the combinational logic block may only be scanned out by performing a sequence of operations to propagate the output signal to a scan cell. In an integrated circuit, the complexity of determining the stimulus to be applied to these sequential circuits can be burdensome. In addition, it may not be possible or practical to apply the desired input combinations or retrieve the sampled output values using this technique. Thus, fault coverage is typically compromised.
What is needed is a method and apparatus to reduce die area by using scan cells at selected inputs and outputs of combinational logic blocks while still providing high fault coverage. What is needed is a method and apparatus to allow the use of scan cells at selected inputs and outputs of combinational logic blocks without the complex and time-consuming use of sequential test generation.